Recently, a low power semiconductor memory or a high capacity semiconductor memory has been used. In conventional memory cells used in a semiconductor memory, resistors are used as load impedances of flip-flop transistors which are used in the memory cells, and also, an insulation between transistors is required, so that the conventional memory cells are large in size. Therefore, a memory chip is also large in size and the density of the memory chips which are included in one wafer can not be increased, so that the cost of a semiconductor memory is expensive.
For the purpose of obtaining memory cells having small dimensions, memory cells using integrated injection logic are used.
At present, memory cells which are constituted by integrated injection logic are important, because such memory cells can be formed with high integration density. Such memory cells are disclosed, for example, in the articles "Write Current Control and Self Powering in a Low Power Memory Cell", IEEE, SSC, Jun., 1973, and "Superintegrated Memory Shares Functions on Diffused Islands", Electronics, Feb. 14, 1972, p83-p86. The former discloses a method of controlling a write current to the integrated injection logic memory cell and the latter discloses a basic idea with respect to the integrated injection logic memory cell.
As disclosed in the above mentioned articles, the integrated injection logic memory cell comprises a pair of first and second transistors which have emitters comprising an injector which are commonly connected to a word line W+, said first and second transistors having a first polarity, a pair of third and fourth transistors which have their collectors connected to collectors of the first and second transistors, respectively the base of the third transistor being connected to the collector of said fourth transistor and the base of the fourth transistor being connected to the collector of said third transistor, both the third and fourth transistors having a second polarity, and a bulk that is a word line W- which is connected to the bases of the first and second transistors and to the emitters of the third and fourth transistors.
The integrated injection logic memory cells are arranged as the memory array. In these integrated injection logic memory cells, the word line W- is formed as the bulk, and the bulk usually consists of two n type layers, an epitaxial layer and a buried layer. The epitaxial layer is formed on the buried layer which has higher conductivity than the epitaxial layer. Therefore, the bulk, that is, the word line W- has a larger resistance than a metallic wire, and this resistance exists between each cell.
When the bulk is used as the word line W- which supplies the hold current, the characteristics of the cells are different in accordance with the positions of the cells in the line of the array. In other words, in the conventional integrated injection logic memory, the hold current source is provided at only one end of the word line W-. Therefore, injection currents which are supplied to the cells near the end of the word line vary according to the bulk resistance, so that uniform distribution of the injection currents to the memory cells cannot be obtained. Therefore, in the memory cell arranged near the end of the word line, a write threshold current Iwth increases and, also, the width of the write pulse increases.